Over the past 30 years, anti-fuse technology has attracted significant attention of many inventors, IC designers and manufacturers. An anti-fuse is a structure alterable to a conductive state, or in other words, an electronic device that changes state from not conducting to conducting. Equivalently, the binary states can be either one of high resistance and low resistance in response to electric stress, such as a programming voltage or current. There have been many attempts to develop and apply anti-fuses in the microelectronic industry, where many anti-fuse applications to date can be seen in FGPA devices manufactured by Actel and Quicklogic, and redundancy or option programming used in DRAM devices by Micron.
An anti-fuse memory is one type of one-time programmable (OTP) memory in which the device can be permanently programmed (electrically) with data once. This data is programmed by an end user for a particular application. There are several types of OTP memory cells which can be used. OTP memories provide users with a level flexibility since any data can be programmed.
Because of its low manufacturing cost, anti-fuse memory can be utilized in all one-time programmable applications, from low cost RF-ID (radio frequency identification) tag applications to automotive and security applications. RF-ID tagging applications are gaining more acceptance in the industry, particularly in sales, security, transport, logistics, and military applications for example. The simplicity and full CMOS compatibility anti-fuse memory allows for application of the RF-ID tag concept to integrated circuit manufacturing and testing processes. Therefore, IC manufacturing productivity can be increased by utilizing anti-fuse memory in combination with an RF communication interface on every wafer and/or every die on the wafer allowing for contact-less programming and reading chip specific or wafer specific information during IC manufacturing and packaging, as well as during printed circuit board assembly.
FIG. 1 is a circuit diagram of a known anti-fuse memory cell, while FIGS. 2 and 3 show the planar and cross-sectional views respectively of the anti-fuse memory cell shown in FIG. 1. The anti-fuse memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. Anti-fuse device 12 is considered a gate dielectric breakdown based anti-fuse device. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer, is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses should be reliable while simple to manufacture with a low cost CMOS process.
The anti-fuse memory cell of FIGS. 1 to 3 can be programmed by biasing the bitline BL and Vcp to voltage levels that result in an electrical field being formed across the thin gate oxide 20. The access transistor is turned on by driving wordline WL to a positive voltage level. This electrical field should be high enough such that a conductive link is formed in the thin gate oxide 20, thereby effectively electrically coupling top plate 16 to the active area under thin gate oxide 20. Therefore, the presence or absence of such a conductive link can represent logic 0 or 1 levels. To read the cell, Vcp is driven to a positive read voltage, and if a conductive link is present, the bitline BL will receive a current or charge from Vcp via the conductive link. It is assumed that WL is driven to a positive voltage during the read operation. This current or charge can be sensed to provide an indication of the logic state stored by the anti-fuse memory cell.
Ideally, an unprogrammed memory cell, or a memory cell that is not intended to be programmed, behaves like an open circuit when the conductive link is absent. Unfortunately defects in the gate oxide, such as thin gate oxide 20 for example, can occur during semiconductor manufacturing and allow tunneling current to flow through these defects during read operations. This tunneling current is exponentially dependent on the voltage applied by Vcp, and more significantly, the impact of the tunneling current on thin gate oxide 20 is cumulative. More specifically, the current flowing through the defects becomes greater with time, eventually causing the thin gate oxide 20 to break down. The gate oxide breakdown occurs when a critical amount of an electrical charge is passed through the thin gate oxide 20. Theoretically, the total charge accumulated in the gate oxide, referred to as QB, is equal to a value of the tunneling current referred to as itunnel, multiplied by the access time referred to as tACC, and the number of cycles N where N is an integer number. If the total charge, QBD, passed though the gate oxide exceeds a critical value, the gate oxide breakdown begins to take place.
Therefore, it is possible that anti-fuse memory cells that were not programmed eventually develop gate oxide breakdown during normal use. This means that the data provided by such a memory cell is incorrect since it was intended to be an unprogrammed cell which now behaves as a programmed cell. Accordingly, it is desirable to provide a technique for retaining the unprogrammed state of anti-fuse memory cells.
Even before delivery to end users, the manufacturer of the memory may encounter defects that render the memory device useless because too many cells cannot be used. This will reduce manufacturing yield, and increase costs. Therefore, there is a need to improve the reliability of anti-fuse memories.